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AN708 vishay siliconix document number: 70581 www.vishay.com faxback 408-970-5600 1 low-power universal-input power supply achieves high efficiency expanding global markets have created a demand for what have become known as universal-input power supplies that is, power supplies that allow devices to be plugged into wall outlets anywhere in the world. these power supplies must be able to operate directly from 100-, 110-, and 220-v ac power lines without the use of selector switches or jumpers. a power supply with the ability to operate under such conditions while remaining cost-effective is now becoming a necessity. in the under 30-w power range, meeting the above requirements while maintaining high efficiency has been a challenge. add to this the need to meet various international safety standards, and the circuit designer has his hands full. the demands of low-power universal-input power supplies are met by the si9120 pulse width modulation (pwm) controller from vishay siliconix. using the si9120, the flyback circuit presented in this application note demonstrates that designing universal-input supplies can be a simple task. for the low power levels that are of interest here (under 30 w), the discontinuous-mode (dcm) flyback converter is the preferred topology. the biggest advantage of this topology is simplicity. the parts count in the power path cannot get any lower. the peak-to-average primary current ratio in a dcm flyback is high relative to other topologies; however, at low power levels, this is not a serious drawback. on-state losses are minimal. magnetics are small. also, the transformer reset voltage is set by the minimum input voltage and remains fairly constant as the line voltage changes. as a result, a 600-v mosfet proves adequate, even with ac inputs up to 300 v rms. the dcm flyback converter, when operated under current-mode control, provides a natural input volt-second limit, which helps keep the drain voltage from getting out of control during line or load transient conditions. also, today's power mosfets are able to withstand avalanche current many times greater than a low power circuit can typically deliver (see appendix a). as such, the mosfet will serve as a clamp for the occasional spike which may result from a short circuit or extreme load transient. cross regulation is fairly good, especially if leakage inductance between windings can be kept low. [1] in a universal-input application, meeting vde input-to-output isolation requirements is essential. depending on the end product, this can be as high as 3750-v rms, primary to secondary a figure that is totally inconsistent with the desire to achieve low leakage inductance. as a result, cross regulation between primary and secondary- referenced windings will be poor. this complicates the regulation of the primary-side bootstrap winding used to avoid secondary-to-primary feedback across the isolation boundary. the addition of a simple spike-blanking circuit solves the problem (see an707, adesigning low-power off-line flyback converters using the si9120 switchmode controller ico). when using the si9120 for universal-input applications, it is recommended that a bootstrap winding be employed. while not strictly necessary, the power dissipation and chip temperature are higher if bootstrapping is not utilized. as an example, at v in = 400 v dc and i cc = 1.5 ma, the power dissipation on the chip without a bootstrap is 600 mw. if a 10 v bootstrap supply is used, the dissipation is only 15 mw. this becomes more of a concern as the gate charge requirements of the power mosfet increase, since the value of i cc for the controller is largely dependent on gate drive demands. another advantage of the dcm flyback converter is its single-pole loop response. this makes compensating the feedback loop comparatively simple. in addition, transient response can be quite good in dcm flyback converters. it is possible (though not practical in a closed-loop system) to slew the power stage from no load to full load in only one switching cycle.
the circuit shown in figure 1 is an 11.1-w, 3-output off-line supply. the input voltage is specified from 90- to 260-v ac. outputs are +5 v at 1.5 a, +12 v at 150 ma, and 12 v at 150 ma. the design features full vde isolation, primary side regulation, and true foldback current limiting. operating frequency is 100 khz. dcm flyback operating principles are generally well understood and will not be presented here. refer to vishay siliconix application note an707 for a detailed design example. references 2 and 3 are also recommended. sizing the input capacitor and rectifiers for universal input requires more thought than for comparable single-input converters. keep in mind that while the maximum input voltage occurs at high-input line, the maximum current stresses will occur at low line. this implies that the input capacitor value must be sized at low line while the voltage rating is dictated by the high-line condition. the bridge rectifier should be rated at 600-v dc minimum. the rms current rating is calculated below.
AN708 vishay siliconix www.vishay.com faxback 408-970-5600 2 document number: 70581 figure 1. schematic for universal-input power supply 1n5822 q2 2n7000 c11 4700 pf c10 0.1 f 50 v mur110 d1 + c4 2200 f 16 v c5 0.47 f 50 v ac in 90 260 v ac 50/60 hz c17 0.1 f x l1 8 mh c19 0.0047 f y c8 0.0047 f 450 v + c20 0.0047 f y c18 0.1 f x c7 33 f 450 v t1 mur110 d7 + c21 2200 f 16 v c22 0.47 f 50 v +12 v, 150 ma 12 v, 150 ma rtn rtn 18 97 r2 175 k 13 11 10 14 615 reset v comp fb dis sense out bias osc sd 5 4 16 12 v in v cc v ref osc si9120 r9 2 k r14 390 k r4 10 r3 1 k c15 n/u r5 1.3 q1 smp4n60 c12 1000 pf 100 v c14 1 f 50 v r10 130 k d5 1n4148 d6 1n4148 d4 1n4148 r6 20 /w d2 + c1 2200 f 6.3 v c3 0.1 f 50 v +5 v, 1.5 a rtn r1 10 c6 1000 pf 100 v c2 1000 f 6.3 v + l2 6 h c9 220 pf r7 1.2 k r8 680 r11 68 k r12 8.2 k q3 2n4403 r13 75 k r15 40.2 k c13 4700 pf d3 db105 out in u1 r16 10 k c6 1000 pf d8
AN708 vishay siliconix document number: 70581 www.vishay.com faxback 408-970-5600 3 for the present example: output power = 5.0 v x 1.5 a + 12 v x 0.15 a x 2 = 11.1 w if efficiency is assumed to be 70%, input power = 11.1 w/0.7 = 15.86 w for a little cushion, assume a low-input line voltage of 85 v ac. thus, v dc 85 2 120v dc. assuming a 20-v pk-pk input-capacitor ripple voltage the minimum voltage is = 15.86 w/ 100 v = 0.1586 a v min = 120 v 20 v = 100 v. i in = p in /v dc = 79 f c i dt dv 0.1586 a x 0.01 s 20 v 68 f is a standard value. with 68 f, the ripple voltage is = 23.5 v, an acceptable value. v pp i dt c 0.16 a 0.01 s 68e6f the capacitor voltage rating is calculated: v max 260 v ac x 2 368 v dc. a 400-v capacitor is acceptable. a rating of 450-v dc is preferable if high reliability is required or significant line transients are expected. assuming a power factor of 0.65, the rms input current is = 0.287 a i ac p o h ac (pf) 11.1 w ( 0.7 )( 85 v )( 0.65 ) a 1-a bridge rectifier is more than adequate. the primary inductance value is chosen by analyzing the lowest input voltage case. for a given load, the value of the peak transformer primary current will remain constant regardless of the input voltage. since the primary inductance is fixed, the time to ramp to a given value of current is inversely proportional to input voltage (v = ldi/dt). therefore, low line is where the most time is needed to ramp to the desired primary current. the duty factor limit dictates an on-time limit. after choosing an operating frequency and calculating the peak primary current, a value for primary inductance, l p , can be determined as follows: for 100 khz, period = 10 s. at 50% duty factor, t on(max) = 5 s. = (0.1586 a) (4) i pk = i in x 4 = 0.634 a pk. for v in (dc) = 100 v = 788 h. l v dt i pk ( 100 v )( 5e6 s ) 0.634 a the actual inductance used was 735 h. [for high-volume production applications, the design engineer should consider the worst case tolerances for clock frequency and inductor value.] see an707 for transformer design equations and a fully worked example. the biggest considerations for universal input are related to the additional insulation required to comply with vde isolation specifications. the physical space occupied by the insulation typically reduces the useable fill factor to 25%. furthermore, the increase in leakage inductance caused by large physical separation of the windings has the undesirable effects of creating large voltage spikes on the power mosfet drain, contributing to power losses, and degrading load regulation. barrier tape at window ends will take up a lot of useable space, so a core geometry with a long, low window should be selected to minimize wasted area. this has the added benefit of reducing leakage inductance. (see equation 6.4 of reference 4.) wind the primary first. apply the required insulation, and then wind the secondaries. all secondaries should be wound together with no intervening insulation, if voltage levels allow. optimal cross regulation is achieved in this way. further reductions in leakage inductance can be realized by using interleaved windings. first wind one half of the primary, followed by the secondaries and remaining primary turns. the multiple primaries are usually connected in parallel. the spike blanking circuit described in an707 virtually eliminates the primary-to-secondary leakage inductance problems, at least from the standpoint of the regulation effects. in selecting a power mosfet, the main concerns will be the r ds(on) and the drain voltage ratings. the transformer primary voltage during the off time is v p = (v o + v d ) n p /n s . using the 5-v winding,
AN708 vishay siliconix www.vishay.com faxback 408-970-5600 4 document number: 70581 v p = (5.0 v + 0.4 v)(45 t/3 t) = 81 therefore, v ds(off) = v in(max) + v p = 368 v + 81 v = 449 v. a 600 v mosfet allows for a 150 v spike due to leakage inductance at high line. the rc snubber was sized empirically to keep the peak drain voltage below 600 v. the smp4n60 is the smallest 600 - v device available. at 25 c the r ds(on) is 2.0 . at 100 c, r ds(on) = 1.75 x 2 = 3.5 . the peak drain current was previously calculated at 0.634 a. the maximum rms drain current is given by i rms i pk d 3 1 2 0.634a 0.5 3 0.26 a on-state losses are given by p on = i rms 2 x r ds(on) = (0.26 a) 2 x 3.5 = 237 mw. switching losses are estimated at 350 mw. since the thermal resistance is specified at 80 c/w, a total temperature rise of 47 c is expected. this permits operation up to approximately 50 c ambient temperature, while holding the maximum junction temperature to 100 c. something of more concern for universal-input than for a single-input voltage supply is the range of duty factor to be expected. since the on time varies inversely with input voltage, the high-line on-time can become quite small in a high-frequency converter. for this kind of application, try to keep the minimum on time to not much less than 1 s. this will help minimize noise problems with the current sense. also, be sure to use a non-inductive resistor for the current sense (carbon composition or film type). use of a wire-wound resistor will produce large spikes which have to be filtered out. the dual-delay current-limit comparators of the si9120 will frequently eliminate the need for a current-sense filter altogether. the magnitude of the noise on the current sense voltage will be affected by transformer parasitic capacitances and pcb layout. as such, every design will exhibit slightly different characteristics. careful attention to detail in the magnetics design and construction as well as the board layout is a must. for designs using current-sense resistors in the power mosfet's source leg, note that the gate drive current is aseeno by the sense resistor. in very low-power designs, this can easily exceed the full load sense voltage causing severe noise problems. adding a fairly large-value gate resistor will help in this case. also, an rc current-sense filter becomes much more important. foldback current limiting is provided by q3 and its associated components. under normal operating conditions, diode d6 keeps c13 charged to v cc . hence, q3 is biased off. in the event of a short circuit on any output, all winding voltages are clamped low. this causes the voltage on c13 to drop to a level set by divider r10 and r11. v cc is held at 8.6 v by the si9120's start-up regulator. the current set by the value of r12 flows through q3 and r3, and causes the voltage on pin 4 to rise. since a peak threshold of 1.2 v is internally set on pin 4, the voltage required across r5 to terminate a pulse is reduced by an amount equal to the drop on r3. i d = {1.2 - (i q3 )(r3)}/r5. thus as i q3 increases, i d decreases. see figure 2a for foldback operating waveforms. the foldback circuit will not perform correctly without the spike blanking circuit. the leakage spike will peak charge c13 even with a shorted load. however, the foldback function is completely optional and all associated components can be eliminated if a lower cost supply is desired.

data compiled on the test circuit appear in table 1. combined line and load regulation measures 2.7%, well within a 5% specification. measured efficiency is 73.4% with no effort at optimization. a detailed loss assessment could, no doubt, offer some improvements. pulse load tests show reasonable transient response, and phase margin is measured at 60 degrees. for details on how to close the feedback loop, refer to vishay siliconix application notes an713 and an707. all data taken with dc input source to ensure stable readings.

full load: v in (dc) i in (ma) +5 v +12 v 12 v 100 v 143.9 4.974 12.64 12.50 200 v 72.3 5.014 12.76 12.61 300 v 48.9 5.027 12.79 12.65 385 v 39.4 5.049 12.81 12.67 half load: 100 v 78.0 5.153 12.99 12.83 200 v 40.3 5.205 13.10 12.96 300 v 27.9 5.235 13.12 12.97 385 v 23.0 5.254 13.14 13.01

5 v +12 v 12 v 60 mv 45 mv 40 mv note: worst case over full line-voltage range.
AN708 vishay siliconix document number: 70581 www.vishay.com faxback 408-970-5600 5 q1 gate drive (5 v/div) q1 gate voltage (100 v/div) q1 drain voltage (100 v/div) q1 drain voltage (100 v/div) figure 2. operating waveforms (all photos full load, v in = 150 v dc) a) b) c) short circuit on 5 v output voltage on u1, pin 4 (current sense) (0.5 v/div) note: 0.8 v dc pedestal caused by voltage on u1, pin 4 (current sense) (0.5 v/div) the foldback circuit. measured efficiency at v in = 300 v dc was 73.4%. during testing, an input capacitor value of as little as 33 f proved adequate versus the design value of 68 f. the low-value capacitor produces an input ripple voltage of 30 v pk-pk. since the primary inductance is slightly lower than the design maximum value, the circuit is still able to maintain regulation with the higher input ripple voltage value. this is a good example of where trade-offs can be made during development programs. by using the larger input capacitance and primary inductance, the peak input current could be reduced slightly, and a slight improvement in efficiency should result. however, a larger input capacitance will decrease the conduction angle of the input rectifiers, and consequently will reduce the input power factor. the priorities of a particular application will determine the optimal approach.
AN708 vishay siliconix www.vishay.com faxback 408-970-5600 6 document number: 70581 the simple universal-input power supply design that has been presented combines economy and performance which should prove more than adequate for the majority of applications. the overall cost of the supply should rival linear regulators of similar power level if heatsink cost is considered. good regulation has been achieved while maintaining the 3750-v ac input-to-output isolation mandated by vde. the si9120 eliminates the need for any external start-up circuitry. also, foldback current-limiting is demonstrated which requires no feedback across the isolation boundary.
the smp4n60 was tested for ability to withstand repetitive avalanche currents and for non-repetitive capability. inductance values of 12 h and 94 h were used. repetitive tests were run at 3 a, with 94 h at 25 c. failure current was measured at 25 c and 100 c. results were as follows: 25 c 100 c 25 c 100 c 4.25 a 2.40 a 7.28 a 6.40 a for the 11.1-w flyback supply presented here, the leakage inductance is specified at 60 h maximum. the maximum drain current is set to approximately 1.0 a. therefore, based on the above data, adequate margin is present to prevent avalanche failure.
a number of performance parameters of the si9120 can be altered by setting i bias to a value other that 15 a. at lower i bias , higher efficiency can be obtained. at higher i bias , lower propagation delays and a wider error amplifier bandwidth are possible. also, if a v cc supply other than 10 v is used, r bias should be something other than 390 k . figure 3 below relates v cc to r bias and typical i bias . the equation given can be used for points not on the graph. 14.0 8.0 515 25 35 45 55 65 7585 9.0 10.0 11.0 12.0 13.0 (v) cc v r = 1 k 750 k 500 k 400 k 300 k 200 k 100 k ma figure 3. relationship of v cc to r bias an typical i bias r bias v cc 2.3v484 i bias i bias 1) liu, k.h., aeffects of leakage inductance on the cross regulation in a discontinuous-mode flyback converter,o proceedings, 1989 high frequency power conference, naples, florida. 2) chryssis, g., ahigh frequency switching power supplies,o mcgraw hill 1984. 3) billings, k., aswitchmode power supply handbook,o mcgraw hill 1989. 4) mclyman, col. w.t., atransformer and inductor design handbook,o mcgraw hill 1988.
AN708 vishay siliconix document number: 70581 www.vishay.com faxback 408-970-5600 7

c1 2200 f, 6.3 v al. electrolytic united chemicon sxc . . . . . . . . . . . . . c2 1000 f, 6.3 v al. electrolytic united chemicon sxc . . . . . . . . . . . . . c3, c10 0.1 f, 50 v ceramic, vishay vitramon vj1206y104kxaat . . . . . . . . . c4, c21 2200 f, 16 v al. electrolytic united chemicon sxc . . . . . . . . . c5, c22 0.47 f, 50 v ceramic, vishay vitramon vj1210y474kxaat . . . . . . . . . c6, c12 1000 pf, 100 v ceramic. vishay vitramon vj1206y102kxbat . . . . . . . . . c7 33 f, 450 v al electrolytic (400 v ok) . . . . . . . . . . . . . c9 220 pf, 100 v ceramic, vishay vitramon vj1206a221kxbat . . . . . . . . . . . . . c11, c13 4700 pf, 100 v ceramic, vishay vitramon vj1206y472kxbat . . . . . . . . c14 1 f, 50 v ceramic, vishay vitramon vj1812y105kxaat . . . . . . . . . . . . c16 75 pf, 500 v ceramic or mica, vishay vitramon vj1206a750kxeat . . . . . . . . . . . . c17, c18 0.1 f, 250 v,ac vde class x2 wima mks 4-r, vishay roederstein f17724102000 . . . . . . . . c8, c19, c20 0.0047 f, 250 v,ac vde class y wima mp3-y, vishay roederstein f17724102000 . . . . d1, d7 mur 110 motorola 1 a 100 v . . . . . . . . . . d2 1n5822 3 a, 40 v schottky . . . . . . . . . . . . . d3 bridge 1 a, 600 v db105 . . . . . . . . . . . . . d4, d5, d6 1n4148 . . . . . . l1 common mode choke renco 1361-2 . . . . . . . . . . . . . . l2 inductor 6 h, 1.5 a, vishay dale ils-1206-6 h 10% . . . . . . . . . . . . . . q1 fet n-channel smp4n60 vishay siliconix . . . . . . . . . . . . . q2 fet n-channel 2n7000 vishay siliconix . . . . . . . . . . . . . q3 2n4403 pnp (or 2n2907) . . . . . . . . . . . . . r1, r4 10 1 / 8 carbon film or metal film, vishay dale tnpw120610r0ft2 . . . . . . . . . . r2 175 k , 1 / 8 w carbon film or metal film, vishay dale tnpw12061753ft2 . . . . . . . . . . . . . r3 1 k , 1 / 8 w carbon film or metal film, vishay dale tnpw12061001ft2 . . . . . . . . . . . . . r5 1.3 1 / 4 w metal film . . . . . . . . . . . . . r6 20 1 / 2 w metal film . . . . . . . . . . . . . r7 1.2 k , 1 / 8 w metal film, vishay dale tnpw12061201ft2 . . . . . . . . . . . . . r8 680 1 / 8 w metal film, vishay dale tnpw12066800ft2 . . . . . . . . . . . . . r9 2 k , 1 / 8 w metal film, vishay dale tnpw12062001ft2 . . . . . . . . . . . . . r10 130 k , 1 / 8 w metal film, vishay dale tnpw12061303ft2 . . . . . . . . . . . . r11 68 k , 1 / 8 w metal film, vishay dale tnpw12066802ft2 . . . . . . . . . . . . . r12 8.2 k , 1 / 8 w metal film, vishay dale tnpw12068201ft2 . . . . . . . . . . . . r13 75 k , 1 / 8 w 1% metal film, vishay dale tnpw12067502ft2 . . . . . . . . . . . . r14 390 k , 1 / 8 w metal film, vishay dale tnpw12063903ft2 . . . . . . . . . . . . r15 40.2 k , 1 / 8 w 1% metal film, vishay dale tnpw12064022ft2 . . . . . . . . . . . . r16 330 1 / 2 w 5% carbon composition . . . . . . . . . . . . t1 schott corp. #67122700 . . . . . . . . . . . . . .

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